Information handling systems such as computers and similar electronic equipment have become essential in the lives of many people today. Many businesses, banks, and governments rely on such systems, particularly computers, as part of their everyday activities. Because of the relatively complex demands placed on these systems, it is essential that said systems be highly reliable and stable. Computers today, for example, are required to run longer, operate at higher frequencies (signal speeds) and exhibit less downtime than at any time in the past. Accordingly, if each component utilized in such systems is designed to last longer and be more reliable, then each system in turn will last longer and be more reliable.
Because circuitized substrates are an essential part of many information handling systems, particularly computers (where several may be found in each), the emphasis on reliability is likewise placed on such substrates. Most components in a computer system are designed by placing semiconductor packages, containing one or more semiconductor chips, onto a PCB or by placing chips directly onto LCCs and connecting the LCCs to the PCB. The PCB circuit lines connect the semiconductor packages or chips together. PCBs can be as simple as a dielectric layer that has lines on one or both sides and one or more packages attached to one or both sides. PCBs used today are generally much more complex, however, and are usually made of metal power and ground planes and several signal planes containing circuit lines sandwiched in an alternative manner between several layers of dielectric material, often with metal lines and pads on the top and bottom surface of the multilayered “sandwich.” Top and bottom conductors may be connected with one other as well as with selected internal circuit layers using conductive “thru holes”, e.g., Plated Through Holes (PTHs).
In a typical method of making a circuitized substrate such as a PCB or LCC, one starting material is usually a sheet consisting of fiberglass and epoxy resin. This is often termed “pre-preg” because the fiber is impregnated with resin during preliminary processing. The resin essentially acts a binder to bind fiber into a board. In place of the fiberglass cloth, it is possible to use compressed paper or other suitable materials, examples of which are described in some of the patents cited below. The basic structure formed at this stage is therefore a flat, rigid or slightly flexible dielectric material that will be fabricated into the final circuitized substrate. This starting material may be laminated with a thin layer of copper on both sides of the board with suitable adhesion. This combination is commonly called copper clad laminate (CCL) if copper is chosen as the outer conductive layer (and if it is laminated to the dielectric layer). These CCLs can either become simple double-sided substrates (having two sides of copper lines) or may be circuitized and thereafter laminated with additional dielectric and/or conductive layers to form larger, thicker multilayered circuitized substrates. In almost all cases, holes are provided (usually by drilling) through these substrates to accommodate electrical connection of the various electronic components that will be attached as well as selected internal conductors. The holes are usually drilled using high speed drilling machines or, of more recent vintage, high speed lasers. In order to make effective electrical connections for this substrate, holes must be formed. When these holes extend through the dielectric, the “plastic” (dielectric material) wall of the hole must be made conductive. This is typically accomplished by a chemical plating process commonly known in the industry as metallization, the process consisting of a relatively complicated series of chemical tanks and rinses and an activating step to apply a thin copper layer to the hole walls. Specifically, in almost all cases, copper electroplating is used to deposit a relatively thick layer of copper in the holes in order to form a suitable copper cross section for carrying current. Copper plating can be followed by tin-lead or tin plating in order to improve solderability, if desired.
Circuitization of the selected conductive layers on the internal dielectric layered structures as well as the outer conductive layers (if used) is typically is accomplished by forming an image of the desired circuit pattern, this image typically formed by applying an organic photoresist coating over the metal layer. Ultraviolet (UV) light is then projected through a mask onto the photoresist, the mask containing a pattern of shapes that block selected parts from the impinging UV light. When using negative photoresist, the areas of the photoresist that are not exposed to the UV light are removed during the subsequent development step. Chemical etching is then used to remove the exposed surface metal. Next, the remaining photoresist is stripped, leaving only the metal pattern.
PCBs made in this manner have substantially become the standard in electronics. Advances in manufacturing processes have made many PCBs and LCCs less expensive, and relatively easier to make. There are still, however, problems associated with these products, many of which are brought on by the aforementioned demands for greater capabilities while offering a smaller scale final product. One of the causes of some problems is a non-optimal (excessive) coefficient of thermal expansion (CTE) mismatch for the overall PCB and the individual layers. Many PCBs and LCCs are generally composed largely of organic materials, and thus tend to have a higher CTE that is not well matched to the CTE of the silicon chip or chips positioned thereon. When trying to reduce the CTE of the PCB/LCC, a variety of dielectrics with lower CTEs are available. However, the effectiveness of using these lower CTE dielectrics is sometimes limited because the power and ground planes, which constitute a significant portion of the PCB, are still composed of a highly electrically conducting metal, typically copper or copper alloy. Copper has a relatively high CTE compared with some of the lower CTE dielectric materials. The relatively high CTE, large amount and high tensile modulus of copper all combine to act to maintain a high composite CTE for the formed (laminated) circuitized substrate. Because the overall CTE is relatively high (compare to the chip(s) which is (are) usually comprised of silicon), the PCB or LCC tends to lengthen and grow in size with increasing temperature. This increase in size means that the chips, packages, lines, and other devices on the surfaces of the PCB or LCC need to expand at the same rate or be able to tolerate the stress caused by the mismatch in size. Sometimes these devices or the electrical connections between them cannot withstand the stress, particularly after repeated temperature cycling.
When solder is used to bond the devices to the substrate (e.g., a chip is connected to the LCC through small solder bumps some of which are called Controlled Collapse Chip Connections (C4) in the art), excessive expansion of the supporting structure may result in damage and even separation of the various solder bonds, thereby rendering the package inoperable for the intended purpose. One effort to prevent this is to use an encapsulation and/or undercoating material which is placed under and around the solder bonds. This adds of course to the total package cost and is not always completely effective when extremely high temperatures might be encountered or if the CTE mismatch is excessive. Further, the chip/PCB or LCC CTE mismatch may result in the assembled package warping, putting tensile stress on the chip to the extent that it might crack and thus be destroyed. Yet another adverse result caused by the CTE differential is shear induced de-bonding, where the dielectric may in fact be torn from the power/ground planes. Shear induced de-bonding exacerbates the CTE-caused cracking mechanisms because the de-bonded dielectric is essentially “floating” and is not connected to the metallic power/ground planes. The periphery of the de-bonded area is, however, typically connected to a metallic plane and tends to move with the metallic plane as the plane lengthens with increasing temperature. Cracking could then occur around the periphery as the periphery moves away from the de-bonded dielectric.
It is thus readily understood from the foregoing that the closer the CTE match between the various elements of a multilayered circuitized substrate including many dielectric and conductive layers and devices such as chips positioned thereon and coupled thereto (especially with solder bonds), the greater the likelihood that a successfully operating product able to meet many of today's rigorous standards will result.
The following U.S. Patents describe various circuitized substrate structures, some including power cores. The citation thereof is not an admission that any are prior art to the instant invention.
In U.S. Pat. No. 5,120,339 for “Method For Fabricating a Low Thermal Expansion Coefficient Glass Fiber-Reinforced Polymer Matrix Composite Substrate And Composite Substrate”, granted Jun. 9, 1992 by Markovich et al., there is described a method of making a composite substrate which comprises the steps of providing a substrate of glass fibers, applying to this substrate a liquid sol-gel wherein said sol-gel comprises a metal alkoxide, sintering the sol-gel to convert it to the glass phase or mixed organic-inorganic gel phase and then applying a coating of a polymer, thus forming the composite substrate. In one example, the polymer is described as being a thermosetting one and the sol-gel is described as being a silica-based sol-gel.
In U.S. Pat. No. 5,418,689 for “Printed Circuit Board Or Card For Direct Chip Attachment And Fabrication Thereof”, granted May 23, 1995 by Alpaugh et al., there is described a PCB product wherein the dielectric substrate can include a thermoplastic and/or thermosetting resin. Thermosetting polymeric materials include epoxy, phenolic base materials, polyimides and polyamides. Examples of some phenolic type materials include copolymers of phenol, resorcinol, and cresol. Examples of suitable thermoplastic polymeric materials include polyolefins such as polypropylene, polysulfones, polycarbonates, nitrile rubbers, ABS polymers, and fluorocarbon polymers such as polytetrafluoroethylene, polymers of chlorotrifluoroethylene, fluorinated ethylenepropylene polymers, polyvinylidene fluoride and polyhexafluoropropylene. The dielectric materials may be molded articles of the polymers containing fillers and/or reinforcing agents such as glass filled polymers. “FR4” epoxy compositions contain 70-90 parts of brominated polyglycidyl ether of bisphenol-A and 10-30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 3-4 parts of dicyandiamide, and 0.2-0.4 parts of a tertiary amine, all parts being parts by weight per hundred parts of resin solids. Another “FR4” epoxy composition may contain about 25 to about 30 parts by weight of a tetrabrominated digylcidyl ether of bisphenol-A having an epoxy equivalent weight of about 350 to about 450; about 10 to about 15% by weight of a tetrabrominated glycidyl ether of bisphenol-A having an epoxy equivalent weight of approximately 600 to about 750 and about 55 to about 65 parts per weight of at least one epoxidized, nonlinear novolak having at least 6 terminal epoxy groups; along with suitable curing and/or hardening agents. A still further “FR4” epoxy composition contains 70 to 90 parts of brominated polyglycidyl ether of bisphenol-A and 10 to 30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 0.8-1 phr of 2-methylimidazole. Still other “FR4” epoxy compositions employ tetrabromobisphenol-A as the curing agent along with 2-methylimidazole as the catalyst.
In U.S. Pat. No. 5,574,630 for “Laminated Electronic Package Including A Power/Ground Assembly”, granted Nov. 12, 1996 by Kresge et al., there is described a power/ground structure and associated circuitized substrate in which the coefficient of thermal expansion of the power/ground structure and associated substrate are closely matched to each other. The substrate is formed of organic electrically insulating material having electrical circuitry thereon which carries an integrated circuit chip. The power/ground assembly is formed of alternating layers of organic insulating material and at least two layers of electrically-conducting material, typically copper, one of the layers of electrically-conducting material forming a power connection and another layer of the electrically-conducting material forming a ground plane. There is also at least one additional layer of a structural material having a relatively high Young's Modulus and a CTE of less than about 10 ppm/degree C. Invar or copper-clad Invar are described as preferred materials for this structure. The electrically conducting copper material and the Invar are selected in thickness and number such that, together with the electrically insulating material, the composite CTE of the power/ground structure closely matches that of the substrate.
In U.S. Pat. No. 5,620,782 for “Method Of Fabricating A Flex Laminate Package”, granted Apr. 15, 1997 by Davis et al., there is described a parallel processor packaging structure and a method for manufacturing the structure. The structure is described as comprising flexible strips, which are discrete subassemblies. These subassemblies are themselves a laminate of at least one internal power core, at least one signal core, with a layer of dielectric there-between. The dielectric is a polymeric dielectric having a dielectric constant less than 3.5, as a polyimide or a perfluorocarbon polymer, or, in a preferred exemplification, a multi-phase composite of a polymeric dielectric material having a low dielectric constant and having a low dielectric constant, low coefficient of thermal expansion material dispersed there-through. Preferably the composite has a dielectric constant less than 3.5, and preferably below about 3.0, and in a particularly preferred embodiment below about 2.0. This is achieved by the use of a low dielectric constant pefluorocarbon polymer matrix, filled with a low coefficient of thermal expansion and preferably low dielectric constant filler. The perfluorocarbon polymer is chosen from the group consisting of perfluoroethylene, perfluoroalkoxies, and copolymers thereof. The dispersed low dielectric constant material is a low dielectric constant, low coefficient of thermal expansion, particulate filler. Exemplary low dielectric constant particulate filler are chosen from the group consisting of silica particles, silica spheres, hollow silica spheres, aluminum oxide, aluminum nitride, zirconium oxide, titanium oxide, and the like. The power core may be a copper foil, a molybdenum foil, or Copper-Invar-Copper (CIC) laminate foil.
In U.S. Pat. No. 5,652,055 for “Matched Low Dielectric Constant, Dimensionally Stable Adhesive Sheet”, granted Jul. 29, 1997 by King et al., there is described an adhesive sheet (or “bond ply”) material suitable to serve as adhesive layers in a variety of adhesive applications, such as in circuit board laminates, multi-chip modules, and in other electrical applications. The adhesive sheet is described as being constructed from an expanded PTFE material. Preferably, the material is filled with inorganic filler and is constructed as follows: A ceramic filler material is incorporated into an aqueous dispersion of dispersion-produced PTFE. The filler in small particle form is ordinarily less than 40 microns in size, and preferably less than 15 microns. The filler is introduced prior to co-coagulation in an amount that will provide 10 to 60%, and preferably 40 to 50% by weight filler in the PTFE, in relation to the final resin-impregnated composite. The filled PTFE dispersion is then co-coagulated, usually by rapid stirring. The coagulated filled PTFE is then added. The filled material is then lubricated with a common extrusion lubricant, such as mineral spirits or glycols, and then extruded. The extrudate is usually calendered, and then rapidly stretched 1.2 to 5000 times, preferably 2 times to 100 times, per this patent, at a stretch rate of over 10% per second, at a temperature of between 35 degrees C. and 327 degrees C. The lubricant can be removed from the extrudate prior to stretching, if desired. The resulting expanded porous filled PTFE is then imbibed with adhesive by dipping, calendaring, or doctor blading on a varnish solution of about 2% to 70% adhesive in solvent. The wet composite is then affixed to what is referred to as a “tenter” frame, and subsequently “B-staged” at or about 165 degrees C. for 1 to 3 minutes. The resulting sheet adhesive typically consists of: (a) 9 to 65 weight percent PTFE; (b) 9 to 60 weight percent inorganic filler, in the form of particulate; and (c) 5 to 60 weight percent adhesive imbibed within the porous web structure.
In U.S. Pat. No. 5,847,327 for “Dimensionally Stable Core For Use In High Density Chip Packages”, granted Dec. 8, 1998 by Fischer et al., there is described a dimensionally stable core for use in high density chip packages. The stable core is a metal core, preferably copper, having clearance holes therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through holes are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided, then the holes do not extend through the clearance holes in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. Lasers are used to form the through holes. Alternating layers of copper and a dielectric comprised of adhesive, filler and expanded poly-tetrafluoroethylene (ePTFE) are also described.
In U.S. Pat. No. 6,073,344 for “Laser Segmentation of Plated Through-Hole Sidewalls To Form Multiple Conductors”, granted Jun. 13, 2000 by Japp et al., there is described a method for generating multiple conductor segments within a PTH of a PCB which utilizes laser light to define the segmented surfaces bounding a hole in the PCB. Two embodiments of this method are a subtractive process and an additive process. The subtractive process starts with a PTH and uses a laser to remove vertical strips of the PTH conductive lining to form multiple conductive segments. The additive process applies a seeding material to a bare hole, removes vertical strips of the seeding material via laser scanning, and applies an electrically conductive material to the seeded surfaces to form multiple conductive segments.
In U.S. Pat. No. 6,259,037 for “Polytetrafluoroethylene Thin Film Chip Carrier”, granted Jul. 10, 2001 by Feilchenfeld et al., there is described an organic chip carrier particularly useful with “flip chips” (typically bonded onto a package top layer using the aforementioned C4 process). The carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about two mils or less and a space between lines of preferably about 1.1 mils or less. Preferably, the dielectric layer is free of woven fiberglass. The coating, referred to as a “conformal” coating, preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. This patent further describes “compensators” which are three layered structures comprised of a first layer of copper, a second layer of 36% nickel-63% iron alloy (which has a CTE of close to zero in the operating layer of the carrier), and a third layer of copper. Preferably a compensator comprises 75% of a 36% nickel-63% iron alloy, and 25% copper. A suitable 36% nickel-63% iron alloy is available under the trademark Invar, from Texas Instruments. Alternatively, the compensator is formed of a single metal such as Invar. The choice of the material for the compensator, together with the choice of material for the dielectric, allegedly controls the CTE of the carrier. Preferably the compensator has a thickness of from about 0.001 to about 0.009 inches, preferably about 0.006 inches. The ground planes may be formed of copper or Copper-Invar-Copper (CIC) or other conductive material as is well known.
In U.S. Pat. No. 6,323,436 for “High Density Printed Wiring Board Possessing Controlled Coefficient of Thermal Expansion With Thin Film Redistribution Layer”, granted Nov. 27, 2001 by Hedrick et al., PCBs are prepared by first impregnating a non-woven aramid chopped fiber mat or a thermoplastic liquid crystalline polymer (LCP) paper instead of the reinforcement typically used in the electronics industry, described in this patent as a woven glass fabric. This aramid reinforcement matte is comprised of a random (in-plane) oriented mat of p-aramid (poly (p-phenylene terephthalamide)) fibers comprised of Kevlar (Kevlar is a registered trademark of E. I. duPont deNemours and Company), and has a dielectric constant of 4.0 as compared to 6.1 for standard E-glass cloth. The lower permittivity of the non-woven aramid reinforcement provides for faster signal propagation, allowing increased wiring density and less crosstalk, which becomes increasingly important for high I/O chips and miniaturization. Since the p-aramid fibers are transversely isotropic and have an axial CTE of about −3 to about −6 ppm/degree Celsius (hereinafter C.) when combined with a thermosetting resin, the final composite described in this patent is said to possess a CTE which can be controlled and adjusted to match that of silicon or semiconductor chips in the range of about 3 to about 10 ppm/degree C. The thermoplastic liquid crystal polymer (LCP) paper is a material called Vecrus (Vecrus is a trademark of Hoechst Celanese Corp.), which uses the company's Vectra polymer as part thereof (Vectra also being a trademark of Hoechst Celanese Corp.). According to this patent, the paper has a dielectric constant of 3.25, a dissipation factor of 0.024 at 60 Hertz (Hz), a UL 94-V rating and an in-plane CTE of less than 10 ppm/degree. C. The alleged advantages of this material over the aramid mat are the lower dielectric constant and very low moisture absorption, allegedly less than 0.02%. The non-woven aramid or LCP paper is used in conjunction with a thermosetting resin to form the final composite substrate. Examples of thermosetting resins useful in this patent include epoxy, cyanate ester, bismaleimide, bismaleimide-triazine, maleimide or combinations thereof. The resin-impregnated low CTE reinforcement is then partially cured to a “B”-stage to form the pre-preg material, and then the pre-preg material is cut, stacked, and laminated to form a sub-composite with exterior copper sheets.
In U.S. Pat. No. 6,329,603 for “Low CTE Power and Ground Planes”, granted Dec. 11, 2001 by Japp et al., there is described various conductive materials that have low CTEs and that are used for power and ground plane structures. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in the individual state thereof and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a circuitized substrate, or laminated into a core which is then laminated with other planes/cores into a circuitized substrate. Examples of such substrates include PCBs and LCCs some examples of which are simply referred to as chip carriers. This patent describes using a conductive fiber layer in which a preferred method of making this layer is to add 40 percent by volume of copper powder to a fiber or fiber/resin layer. During lamination, the copper should distribute evenly throughout the fiber layer. Other conductive fillers may be used, along with other types of layer materials.
In U.S. Pat. No. 6,344,371 for “Dimensionally Stable Core For Use In High Density Chip Packages and a Method of Fabricating Same”, granted Feb. 5, 2002 by Fischer et al., there is described a method for forming a dimensionally stable “core” for use in a chip package, the method comprising the steps of forming a metal layer with clearance holes therein, placing a first dielectric layer on a top surface of the metal layer and placing a second dielectric layer on a bottom surface of the metal layer, these first and second dielectric layers each comprising an expanded poly-tetrafluoroethylene material having an initial void volume and a mean flow pore size, and a mixture substantially evenly distributed throughout this initial void volume containing a particulate filler and an adhesive resin. The particulate filler is described as being a collection of individual particles having an average particle size wherein a ratio of the mean flow pore size to the average particle size is greater than a specified number. The method further includes placing a metal cap layer on each of, and in direct contact with, the top surface of one dielectric layer and the bottom surface of the other dielectric layer.
In U.S. Pat. No. 6,465,084 for “Method and Structure For Producing Z-Axis Interconnection Assembly of Printed Wiring Board Elements”, granted Oct. 15, 2002 by Curcio et al., there is described a method of forming a “core” and forming a composite wiring board (substrate). The core has an electrically conductive coating on at least one face thereof. At least one opening is formed through the structure extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.
In U.S. Pat. No. 6,638,607 for “Method and Structure For Producing Z-Axis Interconnection Assembly of Printed Wiring Board Elements”, granted Oct. 28, 2003 by Curcio et al., there is described a method of forming a composite wiring board, using a “member.” The member includes a dielectric substrate. Adhesive tape is applied to at least one face of this substrate and at least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.
In U.S. Pat. No. 6,645,607 for “Method and Structure For Producing Z-Axis Interconnection Assembly of Printed Wiring Board Elements”, granted Nov. 11, 2003 by Curcio et al., there is described a method of forming a “core” for use as part of a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.
In U.S. Pat. No. 6,826,830 for “Multi-layered Interconnect Structure Using Liquid Crystalline Polymer Dielectric”, granted Dec. 7, 2004 by Egitto et al., there is described a multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second dielectric layer. In a second embodiment, first and second substructures are directly bonded, respectively, to first and second opposing surfaces of a dielectric joining layer, with no extrinsic adhesive material bonding the dielectric joining layer with either the first or second substructures.
In U.S. Pat. No. 6,829,823 for “Method of Making a Multilayered Interconnect Structure”, granted Dec. 14, 2004 by Downes, Jr., et al., there is described a method of making a multi-layered interconnect structure in which first and second electrically conductive members are formed on first and second dielectric layers, respectively. The dielectric layers are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, described as comprising a resin of an allylated polyphenylene ether, is formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.
In U.S. Pat. No. 6,887,779 for “Integrated Circuit Structure”, granted May 3, 2005 by Alcoe et al., there is described a semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate is described having a plurality of plated through holes therein and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further includes a ground plane, two pair of signal planes, and two pair of power planes. A ground plane is described a comprising copper-Invar-copper (CIC), signal planes described as comprising copper. The power planes are formed over each of the second dielectric layers, these first power planes also being of copper. In one example, the dielectric layers comprise a PTFE (polytetrafluroethylene) material filled with silicon particles available from Rogers Corporation. In the alternative, the dielectric layers may be any other similar dielectric materials such as epoxy resins, polyimide, polyphenylene ethers, etc.
In U.S. Pat. No. 6,944,946 for “Porous Power and Ground Planes For Reduced PCB Delamination and Better Reliability”, granted Sep. 20, 2005 by Japp et al., a power core is described which comprises a dielectric layer sandwiched between two copper layers. These copper layers may be thicker than copper layers used for circuit layers in other parts of the final circuitized substrate structure to provide extra current carrying capability. In this example, one copper layer becomes a power plane of the final substrate while the other copper layer becomes a ground plane. One or both of these layers may be patterned and may include openings (called clearance openings) therein. These clearance areas prevent the power and ground planes from contacting subsequent plated through holes that are drilled in these locations after the power core has been pressed into a composite and holes have been drilled and plated. A preferred material suitable for use in the power and ground planes is sintered metal. Sintered metal is formed of metal particles that are bonded together under pressure and heat. Sintered metal power planes may be formed by pressing high melt temperature, high electrical conductivity metal particles (such as copper) coated with a low melt metal (such as tin) together under heat and pressure. The tin-coated copper particles fuse together to form an electrically conductive but porous sheet. Additional materials for creating porous, conductive power and ground planes may be loosely referred to as fibrous conductive materials. These preferred additional materials include small wires formed into a sheet (or “fabric”), metallized fabrics (such as polyester), metallized carbon fiber fabric, and metallized glass fibers. Fabrics can further be broken into woven fabric (fabrics having some non-random structure) and random paper fabrics. Random paper fabrics are generally made from fibers placed in random orientations.
In U.S. Pat. No. 7,078,816 for “Circuitized Substrate”, granted Jul. 18, 2006 by Japp et al., there is described a dielectric layer including an epoxy resin material and a filler comprised of particles having a size within the range of from about 200 Angstroms to about 35 microns, these particles comprising from about 10 percent to about 80 percent by volume of the dielectric layer, said first dielectric layer not including continuous fibers, semi-continuous fibers or the like as part thereof and further including a plurality of conductive thru-holes therein having a pattern density of from about 5,000 to about 10,000 holes per square inch of the dielectric layer. The layer is said to have a dielectric constant within the range of from about 3.5 to about 4.0.
In U.S. Pat. No. 7,301,108 for “Multi-layered Interconnect Structure Using Liquid Crystalline Polymer Dielectric”, granted Nov. 27, 2007 by Egitto et al., there is described multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second two signal, one power (2S1P) substructures are directly bonded, respectively, to first and second opposing surfaces of an LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.
In U.S. Pat. No. 7,429,789 for “Fluoropolymer Dielectric Composition For Use In Circuitized Substrates and Circuitized Substrate Including Same”, granted Sep. 30, 2008 by Japp et al., there is described a dielectric composition adapted for forming a dielectric layer for use in circuitized substrates, this dielectric composition comprising first and second fluoropolymers, the first fluoropolymer having a high melting point from 300 degrees Celsius to 350 degrees Celsius and the second fluoropolymer having a low melting point from 200 degrees Celsius to 280 degrees Celsius. The composition further includes first and second inorganic fillers, the first inorganic filler having a high thermal conductivity from 600 W/m.K degrees to 2000 W/m.K degrees and the inorganic second filler having a low thermal conductivity from 5 W/m.K degrees to 400 W/m.K degrees.
The resulting dielectric layer including this dielectric composition is said to have a dielectric constant of from about 2.8 to about 3.6.
In U.S. Pat. No. 7,508,076 for “Information Handling System Including A Circuitized Substrate Having A Dielectric Layer Without Continuous Fibers”, granted Mar. 24, 2009 by Japp et al., there is described an information handling system having as part thereof a circuitized substrate with a first layer of dielectric material including a resin material with a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer.
As understood from the following, the present invention defines a new power core structure for use in circuitized substrates such as PCBs and LCCs and a method of making such a power core. The invention further defines the package structures in which such cores are used. These packages, as a result of the power core taught herein, are able to assure a proper match between CTEs of the individual elements of package structure, thus assuring a reliable product capable of successfully performing for extended periods of time and of meeting today's rigorous standards.
It is believed such a power core, method of making same, and circuitized substrate package utilizing one or more of such cores will represent a significant advancement in the art.